A Case for MLP-Aware Cache Replacement
Yale N Patt, Onur Mutlu, Daniel N Lynch, Moinuddin K Qureshi
|
Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches
Todd C Mowry, Phillip B Gibbsons, Michael A Kozuch, Onur Mutlu, Vivek Seshadri, Gennady Pekhimenko
|
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
Yale N Patt, Moinuddin K Qureshi
|
Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture
Onur Mutlu, Lavanya Subramanian, Jamie Liu, Vivek Seshadri, Yoongu Kim, Donghyuk Lee
|
Self Optimizing Memory Controllers: A Reinforcement Learning Approach
Rich Caruana, Jose F Martinez, Onur Mutlu, Engin Ipek
|
Scalable high performance main memory system using phase-change memory technology
Jude A Rivers, Vijayalakshmi Srinivansan, Moinuddin K Qureshi
|
A sort-based deferred shading architecture for decoupled sampling
Jacob Munkberg, Robert Toth, Petrik Clarberg
|
Architecture Considerations for Tracing Incoherent Rays
Tero Karras, Timo Aila
|
Light Field Rendering
Pat Hanrahan, Marc Levoy
|
Decoupling Algorithms from Schedules for Easy Optimization of Image Processing Pipelines
Fredo Durand, Saman Amarasinghe, Marc Levoy, Sylvain Paris, Andrew Adams, Jonathan Ragan-Kelley
|
