Optimizing pipelines for power and performance
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
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Instruction issue logic for high-performance, interruptable pipelined processors
G. S. Sohi, S. Vajapayem
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The design space of register renaming techniques
Dezs{\"o} Sima
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The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
M. S. Hrishikesh, Norman P. Jouppi, Keith I Farkas, Premkishore Shivakumar, Doug Burger, Stephen W. Keckler
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Scalable Hardware Memory Disambiguation for High ILP Processors
Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
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Vector vs. superscalar and {VLIW} architectures for embedded multimedia benchmarks
Christoforos E. Kozyrakis, David A. Patterson
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Understanding sources of inefficiency in general-purpose chips
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Mark Horowitz, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis
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Towards an Elastic Distributed SDN Controller
Advait Dixit
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Kandoo: A Framework for Efficient and Scalable Offloading of Control Applications
Soheil Hassas Yeganeh
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Debugging the Data Plane with Anteater
Haohui Mai
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