Memory Scaling: A Systems Architecture Perspective
by Onur Mutlu
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| url: | http://www.ece.cmu.edu/~ece740/f13/lib/exe/fetch.php?media=memory-scaling_memcon13.pdf | | abstract: | The memory system is a fundamental performance
and energy bottleneck in almost all computing systems. Recent
system design, application, and technology trends that require
more capacity, bandwidth, efficiency, and predictability out of
the memory system make it an even more important system
bottleneck. At the same time, DRAM technology is experiencing
difficult technology scaling challenges that make the maintenance
and enhancement of its capacity, energy-efficiency, and reliability
significantly more costly with conventional techniques.
In this paper, after describing the demands and challenges
faced by the memory system, we examine some promising
research and design directions to overcome challenges posed
by memory scaling. Specifically, we survey three key solution
directions: 1) enabling new DRAM architectures, functions,
interfaces, and better integration of the DRAM and the rest of
the system, 2) designing a memory system that employs emerging
memory technologies and takes advantage of multiple different
technologies, 3) providing predictable performance and QoS to
applications sharing the memory system. We also briefly describe
our ongoing related work in combating scaling challenges of
NAND flash memory. |
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In general, this paper outlined the perspective of systems architecture. It is widely acknowledged that the memory system has restricted to a significant extent the performance of almost all computing systems. At the beginning of this paper, the author described some new trends, demands and possible solution directions in memory system development. Then in the rest of the paper, the author covered his solution ideas in the three directions which are 1) overcoming scaling challenges with DRAM,2) enabling the use of emerging memory technologies,3) design memory systems that provide predictable performance and QoS to apps and users. In addition, some challenges are also described, namely, challenge on new DRAM architecture, novel memory technologies, and predictable performance. In the end, the author also mentioned something concerning flash scaling challenge.
In particular, in the section of the challenge from DRAM architecture, specific areas where improvements could be made are listed. Most of them derive from basic ideas in this area, like reducing DRAM latency, reducing refresh impact and so on. Also, some intriguing memory technologies have been introduced, like PCM and STT-MRAM which though could not replace DRAM completely now but indeed provide a tradeoff. Furthermore, making some reasonable estimation of performance also provides some promising branches where improvements could be made.
It should be observed that as the underlying memory technology nears its scaling limits at the physical level, all the approaches mentioned above will be proved to have great significance.