Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures
Yale N Patt, Moinuddin K Qureshi, Onur Mutlu, M. Aater Suleman
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, Critical Section
, Heterogeneous Cores
Sep 18 2013, 20:29
As Amdahl's law argues, the speedup of a program using multiple processors in parallel computing is limited by the time needed for sequential fraction of the program. The general idea proposed in this paper is that, instead of simply designing chips with same low performance, we leverage high performance core(s) to execute critical sections that not only affect the performance of an application but the scalability of it as well. Part of code that can be executed concurrently will be executed on a bunch of small, low performance cores while the critical section that not only affect the performance of the thread that is going through it but also threads that are waiting for the critical section. Another advantage of this architecture is that it doesn't have to move all the shared data among all the cores that are requesting it. To implement this, we need support from the ISA, compiler, on-chip interconnect OS, and of course, from the hardware. A new set of instructions are introduced to perform remote controls on the larger core. A Critical Section Request Buffer is introduced to manage all the request of critical section from different small cores. False Serialization is also considered and addressed here. The ACS is also able to handle issues like nested critical sections, interrupts and exceptions. From my point of view, the asymmetric design is essentially a design of tradeoff. As long as ACS's performance benefits outweigh its overhead, these tradeoffs are worthwhile. Evaluations show that this approach is a very promising way to over bottlenecks posed by critical sections.
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