#1 posted on Sep 22 2013, 19:39
This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus. The solution a sims at reducing bus traffic and bus wait time. Many computer systems, particularly the ons which use microprocessors, are heavily bus-limited. We seek to integrate the high performance of global directory solutions associated with the inhibition of all ineffective invalidations and the modularity and easy adaptability to microprocessors of Goodman's scheme. In our system, the bus provides a convenient "look" operation with which to solve the read-modify-write problem.
This new coherence algorithm takes advantage of the relatively small amount of data shared between processors without the need for a global table. Its primary advantage is easy expandability and very little performance degradation as a result of it.
The evaluation shows that in general, bus utilization and system performance increases almost linearly with N until the bus reaches saturation. At this point, processor utilization begins to approach a curve proportional to 1/N.