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Multiscalar processors
by T.N. Vijaykumar, Scott E. Breach, Gurindar S. Sohi
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multiscalar (1), instruction level parallelism (1), CFG (1), Speculative Execution (1)
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#1 posted on Sep 24 2013, 15:37
A consequence of this sequencing paradigm is that programs are written with the tacit assuption that instructions will be executed in the same order as they appear in the program. Control dependencies (which appear as conditional branches) present a major obstacle to highly parallel execution because these dependencies must be resolved before all subsequent instructions are known to be valid. To achieve high performance, an ILP processor must attempt to walk through the CFG with high level of parallelism. Branch prediction with speculative execution is one commonly used technique for raising the level of parallelism that can be achieved during the walk. Data that is passed between instructions via registers and memory must be routed correctly by the hardware. To insure a correct execution on an ILP processor, it must appear that instructions among all basic blocks execute in precisely the same sequential order, regardless of what actually transpires. A key issue in a multi scalar implementation is the communication of data and control information among the parallel processing units. The sequential order on the processing units is maintained by organizing the units into a circular queue.
Due to the speculative nature of multi scalar execution, it must be possible to both confirm correct execution as well as as recover from incorrect execution. To facilitate maintaining sequential semantics, a multi scalar processor retires tasks from the circular sue of units in the same order as it assigns with them. To coordinate execution among different tasks, it is necessary to charaterize each task according to the set of values that may be consumed by the task and the set of values that may be produced by the task. The function of the multi scalar hardware is to walk through the CFG, assign tasks to the processing units, and execute these tasks with the appearance of sequential execution. The sequencer determines the next task to be assigned by using information in the task descriptor to predict one of the possible successor tasks. Updates of the data cache are not performed speculatively. Instead, additional hardware, known as an Address Resolution Buffer, is provided to hold speculative memory operations, detect violations of memory dependences, and initiate corrective action as needed. There are many micro architectures, but the invariant that has to be preserved is the appearance of a sequential ordering amongst the instructions, with the register and memory values flowing from earlier task to later tasks.