ResearchIndex

annote:

Subbarao Palacharla (Computer Sciences Department; University of Wisconsin-Madison; Madison , WI 53706

publisher:

ACM Press

year:

1997

pages:

206--218

booktitle:

Proceedings of the 24th Annual International Symposium on Computer Architecture

organization:

ACM SIGARCH and IEEE Computer Society TCCA

note:

Published as 24th Annual International Symposium on Computer Architecture (24th ISCA'97), Computer Architecture News, volume 25, number 5

abstract:

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for feature sizes of 0:8?m, 0:35?m, and 0:18?m. Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future. A microarchitecture that simplifies wakeup and selection logic is proposed and discussed. This implementation puts chains of dependent instructions into queues, and issues instructions from multiple queues in parallel. Simulation shows little slowdown as compared with a completely flexible issue window when performance is measured in clock cycles. Furthermore

month:

jun # "~2--4

series:

Computer Architecture News

address:

Denver, Colorado

volume:

25,2

type:

misc

editor:

Andrew R. Pleszkun and Trevor N. Mudge