Design tradeoffs for the alpha {EV8} conditional branch predictor
by Andr{\'e} Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
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| address: | New York | | editor: | Doug {DeGroot} | | abstract: | This paper presents the Alpha EV8 conditional branch predictor The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressive 8-wide issue out-of-order superscalar microarchitecture featuring a very deep pipeline and simultaneous multithreading. Performance of such a processor is highly dependent on the accuracy of its branch predictor and consequently a very large silicon area was devoted to branch prediction on EV8. The Alpha EV8 branch predictor relies on global history and features a total of 352 Kbits.The focus of this paper is on the different trade-offs performed to overcome various implementation constraints for the EV8 branch predictor. One such instance is the pipelining of the predictor on two cycles to facilitate the prediction of up to 16 branches per cycle from any two dynamically successive, 8 instruction fetch blocks. This resulted in the use of three fetch-block old compressed branch history information for accesing the predictor. Implementation constraints also restricted the composition of the index functions for the predictor and forced the usage of only single-ported memory cells.Nevertheless, we show that the Alpha EV8 branch predictor achieves prediction accuracy in the same range as the state-of-the-art academic global history branch predictors that do not consider implementation constraints in great detail. | | volume: | 30, 2 | | series: | Computer Architectuer News | | month: | sep # "~23 | | type: | inproceedings | | pages: | 295--306 | | year: | 2002 | | publisher: | IEEE Computer Society | | booktitle: | 29th International Symposium on Computer Architecture ({ISCA} 2002), 25-29 May 2002, Anchorage, {AK}, {USA} |
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