All papers
| Implementing Precise Interrupts in Pipelined Processors Smith, Plezskun |
| Increasing Processor Performance by Implementing Deeper Pipelines Sprangle, Carmean |
| An Efficient Algorithm for Exploiting Multiple Arithmetic Units Tomasulo |
| The Microarchitecture of Superscalar Processors Smith, Sohi |
| The Design and Analysis of a Cache Architecture for Texture Mapping Ziyad S. Hakura, Anoop Gupta |
| Prefetching in a Texture Cache Architecture Homan Igehy, Matthew Eldridge, Kekoa Proudfoot |
| Bitmap Algorithms for Counting Active Flows on High Speed Links Cristian Estan, George Varghese, Mike Fisk |
| Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors Onur Mutlu, Jared Stark, Chris Wilkerson, Yale Patt |
| Efficient Runahead Execution: Power-efficient Memory Latency Tolerance Onur Mutlu, Hyesoon Kim, Yale Patt |
| Memory dependence prediction using store sets George Z. Chrysos, Joel S. Emer |